1. Field of the Invention
The present invention relates to a digital signal processing device which performs a variety of digital signal processings.
2. Prior Art
As the conventional digital signal processing devices, the digital signal processor (i.e., DSP) is known. The DSP is advantageous in performing a variety of digital signal processings at high speed. Normally, the DSP contains an arithmetic unit which performs arithmetical operations such as addition and multiplication. As compared to other portions of the DSP, the arithmetic unit is disadvantageous in that the processing speed, particularly the processing speed of the multiplier, is relatively slow. In order to cope with the disadvantage, the pipeline processing is employed to perform the operations.
However, employment of the pipeline processing results in the restriction to the programming for the conventional DSP which uses a plenty of microprograms. In general, the execution speed of the multiplier provided in the arithmetic unit is lower than the execution speed to perform one step of the microprogram; in other words, a certain amount of execution time, which is larger than an execution time required for executing one step of the microprogram, is required to yield a result of multiplication. This means that the result of multiplication cannot be used immediately in the step next to the step which achieves the multiplication instruction. In short, the conventional DSP is disadvantageous in that the processing cannot be performed continuously.
Now, assuming the case where an arithmetical operation for an equation "a.times.b.times.c" is performed under the condition where two steps are required to yield the result of multiplication, for example. In that case, if the multiplication of "a.times.b" is performed in first step, a result of that multiplication can be obtained not in second step but in third step. Therefore, the next multiplication using the number `c` should be performed on the result of the multiplication of "a.times.b", which is retained in a register, in third step or later. For this reason, the second step is useless in terms of the execution of the above arithmetical operation; actually however, the second step can be used for executing another instruction. Since the arithmetic unit, containing the multiplier, employs the pipeline processing, the multiplication instruction can be provided for the second step.
As described above, the conventional DSP suffers from a problem that the programming for the microprogram cannot be made continuously. If the DSP uses a high-speed multiplier which is capable of performing the multiplication within one step, the above problem may be eliminated. However, such multiplier is very expensive in cost. In addition, the above problem can be solved by reducing the number of steps of the microprogram which are carried out in one sampling period. However, this will deteriorate the performability of the DSP because in general, the performability of the DSP is improved by increasing the number of steps of the microprogram to be carried out in one sampling period.
When creating the microprogram for the conventional DSP, the designer should create it by paying attention to the timings to yield the results of multiplication. So, codes of different operations should emerge in turn in the microprogram. This badly affects the readability for the microprogram. In short, it takes much time in debugging the microprogram.